The present invention relates to a semiconductor device and a manufacturing technology thereof, particularly to a technology effective when applied to a semiconductor device having a power supply circuit and a manufacturing method thereof.
A DC-DC converter widely used as one of power supply circuits has a high-side power MOS•FET (Metal Oxide Semiconductor Field Effect Transistor) and a low-side power MOS•FET connected to each other in series. The high-side power MOS•FET has a switching function for controlling a DC-DC converter, while the low-side power MOS•FET has a switching function for synchronous rectification. These two power MOS•FETs perform voltage conversion by being alternately turned ON/OFF while being synchronized with each other.
A non-insulated type DC-DC converter to be used in a power supply circuit of, for example, desktop personal computers, servers and game machines tends to have a larger current and higher frequency with a demand for an increase in the current flowing into a CPU (Central Processing Unit) or the like to be driven and size reductions of passive elements such as choke coil and input/output capacitance. With an advance of a current increase and frequency heightening, however, a conduction loss and a recovery loss of a body diode parasitic to the low-side power MOS•FET increase during the term (dead time term) when both the high-side power MOS•FET and low-side power MOS•FET are turned OFF. In order to overcome this problem, a conduction loss and a recovery loss of the diode are reduced by connecting a Schottky barrier diode (which will hereinafter be abbreviated as “SBD”) to the low-side power MOS•FET in parallel and causing a current to flow through not the body diode but the SBD.
There is a description on a DC-DC converter, for example, in Japanese Unexamined Patent Publication No. Hei 10 (1998)-150140. The DC-DE converter described therein has a structure in which an MOS•FET and an SBD connected in parallel with each other are formed on respective semiconductor dies and these two semiconductor dies are contained in one package (refer to Patent Document 1).
For example, in Japanese Unexamined Patent Publication No. 2003-124436, described is a DC-DC converter in which a semiconductor chip having, formed thereover, a high-side power MOS•FET and a semiconductor chip having, formed thereover, a low-side power MOS•FET and an SBD connected in parallel therewith are contained in one package (Refer to Patent Document 2).
In Japanese Unexamined Patent Publication No. Hei 9 (1997)-102602, described is a semiconductor chip having, formed thereover, a low-side MOS•FET and an SBD connected in parallel therewith, wherein the SBD is formed in an active cell of the low-side MOS•FET (refer to Patent Document 3).    [Patent Document 1] Japanese Unexamined Patent Publication No. Hei 10 (1998)-150140    [Patent Document 2] Japanese Unexamined Patent Publication No. 2003-124436    [Patent Document 3] Japanese Unexamined Patent Publication No. Hei 9 (1997)-102602